1) Add a Layer to BitBake
* Folder Structure
${fsl-release-bsp}/sources/meta-t0040
${fsl-release-bsp}/sources/meta-t0040/conf
${fsl-release-bsp}/sources/meta-t0040/recipes-kernel
${fsl-release-bsp}/sources/meta-t0040/recipes-kernel/linux
${fsl-release-bsp}/sources/meta-t0040/recipes-kernel/linux/files
* ${fsl-release-bsp}/sources/meta-t0040/conf/layer.conf
# We have a conf and classes directory, append to
BBPATHBBPATH .= ":${LAYERDIR}"
# We have a recipes directory, add to
BBFILESBBFILES += "${LAYERDIR}/recipes-*/*/*.bb ${LAYERDIR}/recipes-*/*/*.bbappend"
BBFILE_COLLECTIONS += "t0040"
BBFILE_PATTERN_t0040 := "^${LAYERDIR}/"
BBFILE_PRIORITY_t0040 = "9"
LAYERVERSION_t0040 = "1"
* ${fsl-release-bsp}/sources/meta-t0040/recipes-kernel/linux/linux-imx_%.bbappend
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
SRC_URI += "file://fragment-t0040.cfg"
SRC_URI += "file://imx6ull-t0040.dts"
SRC_URI += "file://imx6ull-t0040-btwifi.dtsi"
# support for TUN / RNDIS / IP_TABLES
do_configure_prepend () {
echo "CONFIG_NETFILTER=y" >> ${B}/.config
echo "CONFIG_NETFILTER_DEBUG=y" >> ${B}/.config
echo "CONFIG_NETFILTER_ADVANCED=n" >> ${B}/.config
echo "CONFIG_TUN=m" >> ${B}/.config
echo "CONFIG_USB_ETH_RNDIS=m" >> ${B}/.config
echo "CONFIG_USB_NET_RNDIS_HOST=m" >> ${B}/.config
echo "CONFIG_NETFILTER_XTABLES=m" >> ${B}/.config
echo "CONFIG_NF_CONNTRACK=m" >> ${B}/.config
echo "CONFIG_NF_TABLES=m" >> ${B}/.config
echo "CONFIG_NF_NAT=m" >> ${B}/.config
echo "CONFIG_NF_NAT_MASQUERADE_IPV4=m" >> ${B}/.config
echo "CONFIG_IP_NF_CONNTRACK=m" >> ${B}/.config
echo "CONFIG_IP_NF_NAT=m" >> ${B}/.config
echo "CONFIG_IP_NF_TARGET_MASQUERADE=m" >> ${B}/.config
cp ${B}/../imx6ull-t0040.dts ${S}/arch/arm/boot/dts/imx6ull-14x14-evk.dts
cp ${B}/../imx6ull-t0040-btwifi.dtsi ${S}/arch/arm/boot/dts/imx6ul-evk-btwifi.dtsi}
* ${fsl-release-bsp}/sources/meta-t0040/recipes-kernel/linux/files/imx6ull-t0040.dts
(file-link : https://drive.google.com/file/d/0B4POblBurRQjM2FMaG1nNnBMSHM/view?usp=sharing)
(file-link : https://drive.google.com/file/d/0B4POblBurRQjM2FMaG1nNnBMSHM/view?usp=sharing)
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx6ull.dtsi"
/ {
model = "Freescale i.MX6 ULL T0040 Board";
compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
chosen { stdout-path = &uart1; };
memory { reg = <0x80000000 0x20000000>; };
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable; size = <0x14000000>;
linux,cma-default;
};
};
pxp_v4l2 { compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; status = "okay"; };
regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>;
reg_gpio_dvfs: regulator-gpio { compatible = "regulator-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dvfs>; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1400000>; regulator-name = "gpio_dvfs"; regulator-type = "voltage"; gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; states = <1300000 0x1 1400000 0x0>; }; };
sound { compatible = "fsl,imx6ul-evk-wm8960", "fsl,imx-audio-wm8960"; model = "wm8960-audio"; cpu-dai = <&sai2>; audio-codec = <&codec>; asrc-controller = <&asrc>; codec-master; gpr = <&gpr>; /* * hp-det = <hp-det-pin hp-det-polarity>; * hp-det-pin: JD1 JD2 or JD3 * hp-det-polarity = 0: hp detect high for headphone * hp-det-polarity = 1: hp detect high for speaker */ hp-det = <3 0>; hp-det-gpios = <&gpio5 4 0>; mic-det-gpios = <&gpio5 4 0>; audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", "Ext Spk", "SPK_LN", "Ext Spk", "SPK_RP", "Ext Spk", "SPK_RN", "LINPUT2", "Mic Jack", "LINPUT3", "Mic Jack", "RINPUT1", "Main MIC", "RINPUT2", "Main MIC", "Mic Jack", "MICB", "Main MIC", "MICB", "CPU-Playback", "ASRC-Playback", "Playback", "CPU-Playback", "ASRC-Capture", "CPU-Capture", "CPU-Capture", "Capture"; };};
&cpu0 { arm-supply = <®_arm>; soc-supply = <®_soc>; dc-supply = <®_gpio_dvfs>;};
&clks { assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <786432000>;};
&gpc { fsl,cpu_pupscr_sw2iso = <0x1>; fsl,cpu_pupscr_sw = <0x0>; fsl,cpu_pdnscr_iso2sw = <0x1>; fsl,cpu_pdnscr_iso = <0x1>; fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */};
&i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay";
mag3110@0e { compatible = "fsl,mag3110"; reg = <0x0e>; position = <2>; };
fxls8471@1e { compatible = "fsl,fxls8471"; reg = <0x1e>; position = <0>; interrupt-parent = <&gpio5>; interrupts = <0 8>; };};
&i2c2 { clock_frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay";
codec: wm8960@1a { compatible = "wlf,wm8960"; reg = <0x1a>; clocks = <&clks IMX6UL_CLK_SAI2>; clock-names = "mclk"; wlf,shared-lrclk; };
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx6ul-evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xa0 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xa0 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xa0 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xa0 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xa0 MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0xa0 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0xa0 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0xa0 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xa0 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0xa0 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xa0 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0xa0 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0xa0
>;
};
pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 >; };
pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 >; };
pinctrl_flexcan1: flexcan1grp{ fsl,pins = < MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 >; };
pinctrl_flexcan2: flexcan2grp{ fsl,pins = < MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 >; };
pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 >; };
pinctrl_i2c2: i2c2grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 >; };
pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 >; };
pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 >; };
pinctrl_qspi: qspigrp { fsl,pins = < MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; };
pinctrl_sai2: sai2grp { fsl,pins = < MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 >; };
pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; };
pinctrl_uart2: uart2grp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 >; };
pinctrl_uart2dte: uart2dtegrp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 >; };
pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 >; };
pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >; };
pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; };
pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 >; };
pinctrl_usdhc2_8bit: usdhc2grp_8bit { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 >; };
pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 >; };
pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 >; };
pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; }; };};
&iomuxc_snvs { pinctrl-names = "default_snvs"; pinctrl-0 = <&pinctrl_hog_2>; imx6ul-evk { pinctrl_hog_2: hoggrp-2 { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 >; };
pinctrl_dvfs: dvfsgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 >; }; pinctrl_lcdif_reset: lcdifresetgrp { fsl,pins = < /* used for lcd reset */ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 >; };
pinctrl_sai2_hp_det_b: sai2_hp_det_grp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 >; }; };};
&lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl &pinctrl_lcdif_reset>; display = <&display0>; status = "okay";
display0: display { bits-per-pixel = <16>; bus-width = <24>;
display-timings { native-mode = <&timing0>; timing0: timing0 { clock-frequency = <9200000>; hactive = <480>; vactive = <272>; hfront-porch = <8>; hback-porch = <4>; hsync-len = <41>; vback-porch = <2>; vfront-porch = <4>; vsync-len = <10>;
hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; }; };};
&pxp { status = "okay";};
&qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; status = "okay"; ddrsmp=<0>;
flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a"; spi-max-frequency = <29000000>; spi-nor,ddr-quad-read-dummy = <6>; reg = <0>; };};
&sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2 &pinctrl_sai2_hp_det_b>;
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, <&clks IMX6UL_CLK_SAI2>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <0>, <12288000>;
status = "okay";};
&uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay";};
&uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; fsl,uart-has-rtscts; /* for DTE mode, add below change */ /* fsl,dte-mode; */ /* pinctrl-0 = <&pinctrl_uart2dte>; */ status = "okay";};
&usbotg1 { dr_mode = "otg"; srp-disable; hnp-disable; adp-disable; status = "okay";};
&usbotg2 { dr_mode = "host"; disable-over-current; status = "okay";};
&usbphy1 { tx-d-cal = <0x5>;};
&usbphy2 { tx-d-cal = <0x5>;};
&usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; keep-power-in-suspend; enable-sdio-wakeup; status = "okay";};
&usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; non-removable; status = "okay";};
&wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,wdog_b;};
* ${fsl-release-bsp}/sources/meta-t0040/recipes-kernel/linux/files/imx6ull-t0040-btwifi.dtsi
/* Nothing because we do not use BT and Wi-Fi */
2) Rebuild the Image
bitbake -c clean linux-imx
bitbake fsl-image-gui
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